جلد 5، شماره 3 - ( 6-1388 )                   جلد 5 شماره 3 صفحات 180-184 | برگشت به فهرست نسخه ها

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S. R. Talebiyan, S. Hosseini-Khayat. Low-Power Adder Design for Nano-Scale CMOS. IJEEE. 2009; 5 (3) :180-184
URL: http://ijeee.iust.ac.ir/article-1-182-fa.html
Low-Power Adder Design for Nano-Scale CMOS. . 1388; 5 (3) :180-184

URL: http://ijeee.iust.ac.ir/article-1-182-fa.html


چکیده:   (10966 مشاهده)
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
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موضوع مقاله: 2-Integrated Circuits: Digital, Analog
دریافت: ۱۳۸۸/۶/۱۷ | پذیرش: ۱۳۹۲/۱۰/۹ | انتشار: ۱۳۹۲/۱۰/۹