Volume 5, Issue 4 (December 2009)                   IJEEE 2009, 5(4): 223-229 | Back to browse issues page

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Abstract:   (5506 Views)
Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the performance of the proposed structure, various tests performed and results compared with standard phase locked loop. The tests and results show the superior performance of the proposed PLL.
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Type of Study: Research Paper | Subject: Analog Circuits
Received: 2009/09/14 | Accepted: 2011/06/19 | Published: 2013/12/30