جلد 5، شماره 4 - ( 9-1388 )                   جلد 5 شماره 4 صفحات 223-229 | برگشت به فهرست نسخه ها


XML Print


Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Miar- Naimi H, Zabihi M. Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm. IJEEE. 2009; 5 (4) :223-229
URL: http://ijeee.iust.ac.ir/article-1-188-fa.html
Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm. . 1388; 5 (4) :223-229

URL: http://ijeee.iust.ac.ir/article-1-188-fa.html


چکیده:   (4250 مشاهده)
Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the performance of the proposed structure, various tests performed and results compared with standard phase locked loop. The tests and results show the superior performance of the proposed PLL.
     
نوع مطالعه: Research Paper | موضوع مقاله: 2-Analog Circuits
دریافت: ۱۳۸۸/۶/۲۳ | پذیرش: ۱۳۹۰/۳/۲۹ | انتشار: ۱۳۹۲/۱۰/۹

ارسال نظر درباره این مقاله : نام کاربری یا پست الکترونیک شما:
کد امنیتی را در کادر بنویسید