Iranian Journal of Electrical and Electronic Engineering
IJEEE
Engineering & Technology
http://ijeee.iust.ac.ir
18
agent2
1735-2827
2383-3890
10.22068/IJEEE
en
jalali
1399
9
1
gregorian
2020
12
1
16
4
online
1
fulltext
en
Modified 32-Bit Shift-Add Multiplier Design for Low Power Application
2-VLSI
VLSI
Research Paper
Research Paper
<div style="text-align: justify;"><span style="font-family:Times New Roman;"><span style="font-size:14px;"><span style="color:#000000;">Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. The multiplier speed usually determines the speed of the processor. Hence in this work, a design of a 32-bit multiplier is proposed by modifying the conventional shift-add multiplier. The proposed structure reduces the power consumed by the technique of minimizing the switching activities in the design. A 32-bit parallel prefix adder based on the modified Ling equation is also proposed to speed up the addition of the partial products in the multiplier. The design is modeled in VHDL and implementation is carried out in CADENCE software with 90 nm and 180 nm CMOS technology.</span></span></span></div>
Shift-Add Multiplier, Parallel Prefix Adder, Low-Power, VLSI Implementation.
487
493
http://ijeee.iust.ac.ir/browse.php?a_code=A-10-3376-1&slc_lang=en&sid=1
R.
Pinto
rohanp@sjec.ac.in
`180031947532846009313`

180031947532846009313
Yes
Department of Electronics and Communication Engineering, St. Joseph Engineering College, Vamanjoor, Mangalore, India.