en 2-VLSI VLSI Research Paper Research Paper <span lang="EN-IN" style="font-size:10.0pt"><span style="font-family:&quot;Times New Roman&quot;,serif">Memristors are a viable future semiconductor memory substitute because of its nanoscale size, quick switching, low power consumption, and CMOS compatibility.</span></span><span lang="EN-IN" style="font-size:10.0pt"><span style="font-family:&quot;Times New Roman&quot;,serif"> CMOS flip-flops face drawbacks like large size, high power use, and charge loss at smaller scales.</span></span><span style="font-size:10.0pt"><span style="font-family:&quot;Times New Roman&quot;,serif"> However, memristors provide a novel approach to the construction of FFs that improves outcomes. In the previous work, the execution of a four-bit PIPO shift register design was demonstrated using a D flip-flop. D Flip-flops are designed with NAND Gates. In this paper, we will improve the performance of flip-flops by using memristors, followed by the performance of D flip-flops and PIPO shift register using the Power Gating Technique. As the Results Session displays the power usage of the NAND Gate. The power consumption of a D flip-flop using the memristor design is 6.182</span></span><span style="font-size:10.0pt"><span style="font-family:&quot;Times New Roman&quot;,serif"> &micro;W, while using the power gating technique, the power usage of D flip-flop is 5.827 &micro;W. For DFF Power reduced by 86.1%, Delay reduced by 47.1% and PDP improved by 99.86% compared to conventional design. The power consumption of a PIPO using the memristor design is 22.52 &micro;W, while using the power gating technique, the power usage of PIPO is 21.28 &micro;W. The power consumption of PIPO circuit is reduced by 98.3% compared with conventional design.</span></span><span style="color:#000000;"><span style="font-size:10pt"><span new="" roman="" times=""><span style="color:#5b9bd5"></span></span></span><br> &nbsp;</span> Flip-flops, NAND Gate, Memristor, Power Gating, Parallel in parallel Out 4056 4056 http://ijeee.iust.ac.ir/browse.php?a_code=A-10-6012-1&slc_lang=en&sid=1 E Vijaya Babu 1800319475328460017609 1800319475328460017609 No Department of ECE, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology, Bachupally, Hyderabad, India G Shanthi shanthi_g@vnrvjiet.in 1800319475328460017608 1800319475328460017608 Yes Department of ECE, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology, Bachupally, Hyderabad, India Ayesha Thabassum Ara 1800319475328460017610 1800319475328460017610 No Department of ECE, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology, Bachupally, Hyderabad, India K V Balaramakrishna 1800319475328460017611 1800319475328460017611 No Department of ECE, Aditya University, Surampalem, India Madhu Nakirekanti 1800319475328460017612 1800319475328460017612 No AVN institute of Engineering and Technology, Hyderabad, India K Narsimha Reddy 1800319475328460017613 1800319475328460017613 No Department of ECE, Vardhaman College of Engineering, Hyderabad, India