Volume 18, Issue 2 (June 2022)
IJEEE 2022, 18(2): 66-78 |
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Abstract: (2063 Views)
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers. Sensitization conditions for the employed ternary multiplexers are introduced. Moreover, static timing analysis and dynamic programming are utilized in the identification of true and false paths of the circuit for obtaining more realistic results in a reasonable time. An event-driven simulation engine is also developed for confirming the sensitization state of the identified paths. Some ternary arithmetic logic circuits are designed to depict the effectiveness of the proposed identification method. Simulation results show the correctness and efficiency of the proposed method.
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- Dynamic sensitization conditions for 2:1 ternary multiplexers presented (that are used in constructing the ternary circuits) are introduced.
- A dynamic programming procedure for identifying the true and false paths of the circuit by using static timing analysis is proposed.
- An event-driven simulation engine is introduced that is utilized in confirming the sensitization state of the identified paths.
- Carry skip adders, which are known to have many false paths, in addition to some other arithmetic circuits are designed by ternary logic as benchmark circuits to depict the effectiveness of the proposed identification algorithm in finding the true and false paths of the circuit.
Type of Study: Research Paper |
Subject:
VLSI
Received: 2021/07/27 | Revised: 2024/05/13 | Accepted: 2022/01/25
Received: 2021/07/27 | Revised: 2024/05/13 | Accepted: 2022/01/25
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