<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING</title>
<title_fa></title_fa>
<short_title>IJEEE</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://ijeee.iust.ac.ir</web_url>
<journal_hbi_system_id>18</journal_hbi_system_id>
<journal_hbi_system_user>agent2</journal_hbi_system_user>
<journal_id_issn>1735-2827</journal_id_issn>
<journal_id_issn_online>1735-2827</journal_id_issn_online>
<journal_id_pii></journal_id_pii>
<journal_id_doi></journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid></journal_id_sid>
<journal_id_nlai></journal_id_nlai>
<journal_id_science></journal_id_science>
<language>en</language>
<pubdate>
	<type>jalali</type>
	<year>1397</year>
	<month>3</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2018</year>
	<month>6</month>
	<day>1</day>
</pubdate>
<volume>14</volume>
<number>2</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa></title_fa>
	<title>Switched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications</title>
	<subject_fa>2-Integrated Circuits: Digital, Analog</subject_fa>
	<subject>Integrated Circuits: Digital, Analog</subject>
	<content_type_fa>Research Paper </content_type_fa>
	<content_type>Research Paper </content_type>
	<abstract_fa></abstract_fa>
	<abstract>&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;color:#000000;&quot;&gt;&lt;span style=&quot;font-size:12px;&quot;&gt;&lt;span style=&quot;font-family:tahoma;&quot;&gt;This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of a PMOS transistor. The proposed structure improves the propagation delay of a circuit and is much suitable for those circuits with high switching factor. Post layout simulation results using TSMC 180&amp;nbsp;nm CMOS technology at 0.2V supply voltage shows 45% improvement in delay as well as 25% less power consumption at the cost of only 53% more occupied area.&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/div&gt;
</abstract>
	<keyword_fa></keyword_fa>
	<keyword>Low Power,High Speed,Sub-Threshold,Body Biasing,Dynamic Threshold,</keyword>
	<start_page>170</start_page>
	<end_page>177</end_page>
	<web_url>http://ijeee.iust.ac.ir/browse.php?a_code=A-10-2275-1&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>M.</first_name>
	<middle_name></middle_name>
	<last_name>Ashraf</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>m.r.ashraf@shahroodut.ac.ir</email>
	<code>180031947532846006439</code>
	<orcid>180031947532846006439</orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation>Faculty of Electrical Engineering and Robotics, Shahrood University of Technology, Shahrood, Iran.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
