Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 A Chaos-Based Communication Scheme Using Proportional and Proportional-Integral Observers 127 139 EN R. Kharel N K. Busawon N Z. Ghassemlooy Y In this paper, we propose a new chaos-based communication scheme using the observers. The novelty lies in the masking procedure that is employed to hide the confidential information using the chaotic oscillator. We use a combination of the addition and inclusion methods to mask the information. The performance of two observers, the proportional observer (P-observer) and the proportional integral observer (PI-observer) is compared that are employed as receivers for the proposed communication scheme. We show that the P-observer is not suitable scheme since it imposes unpractical constraints on the messages to be transmitted. On the other hand, we show that the PI-observer is the better solution because it allows greater flexibility in choosing the gains of the observer and does not impose any unpractical restrictions on the message. Chaotic Synchronization,Duffing Oscillator,P & PI-Observers,Secure Communication, http://ijeee.iust.ac.ir/article-1-80-en.html http://ijeee.iust.ac.ir/article-1-80-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 Adaptive Signal Detection in Auto-Regressive Interference with Gaussian Spectrum 140 140 EN M. R. Moniri Y M. M. Nayebi N A. Sheikhi N A detector for the case of a radar target with known Doppler and unknown complex amplitude in complex Gaussian noise with unknown parameters has been derived. The detector assumes that the noise is an Auto-Regressive (AR) process with Gaussian autocorrelation function which is a suitable model for ground clutter in most scenarios involving airborne radars. The detector estimates the unknown parameters by Maximum Likelihood (ML) estimation for the use in the Generalized Likelihood Ratio Test (GLRT). By computer simulations, it has been shown that for large data records, this detector is Constant False Alarm Rate (CFAR) with respect to AR model driving noise variance. Also, measurements show the detector excellent performance in a practical setting. The detector’s performance in various simulated and actual conditions and the result of comparison with Kelly’s GLR and AR-GLR detectors are also presented. CFAR,GLR Test,Radar Detection, http://ijeee.iust.ac.ir/article-1-81-en.html http://ijeee.iust.ac.ir/article-1-81-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 Multilevel PWM Waveform Decomposition and Phase-Shifted Carrier Technique 150 164 EN R. Naderi N A. Rahmati Y Multilevel PWM waveforms can be decomposed into several multilevel PWM components. Phase-shifted carrier (PSC) is an efficient decomposition technique. In this paper, we have first demonstrated the equality of PSC and alternative phase opposition disposition techniques. Second, we have modified PSC to accommodate other disposition techniques. Third, we have investigated the effects of using asymmetrical carriers on the spectrum of the resulting PWM waveform. Fourth, we have proposed a logical algorithm for decomposing all types of multilevel PWM waveforms. Carrier-Based PWM,Phase-Shifted Carrier,Multilevel Inverters, http://ijeee.iust.ac.ir/article-1-82-en.html http://ijeee.iust.ac.ir/article-1-82-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 Behavioral Modeling and Simulation of Semiconductor Devices and Circuits Using VHDL-AMS 165 175 EN Gh. R. Karimi N and S. Mirzakuchaki Y During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design community, efficient semiconductor device models must be available. In this paper, potential merits of the new IEEE VHDL-AMS standard in the field of modeling semiconductor devices are discussed. The device models for diodes and the principles, techniques, and methodology used to achieve the design of an analytical third generation Spice transistor MOS model named EKV are presented. This is done by taking into account the thermoelectrical effect in VHDL-AMS, and with relevant parameters set to match a deep submicron technology developed in VHDL-AMS. The models were validated using System Vision from Mentor Graphics. Behavioral Models,EKV Transistor,ODAE,Semiconductor Devices,Thermoelectrical Effect,VHDL-AMS, http://ijeee.iust.ac.ir/article-1-83-en.html http://ijeee.iust.ac.ir/article-1-83-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 FACTS Devices Allocation to Congestion Alleviation Incorporating Voltage Dependence of Loads 176 190 EN M. Gitizadeh N M. Kalantar Y This paper presents a novel optimization based methodology to allocate Flexible AC Transmission Systems (FACTS) devices in an attempt to improve the previously mentioned researches in this field. Static voltage stability enhancement, voltage profile improvement, line congestion alleviation, and FACTS devices investment cost reduction, have been considered, simultaneously, as objective functions. Therefore, multi-objective optimization without simplification has been used in this paper to find a logical solution to the allocation problem. The optimizations are carried out on the basis of location, size and type of FACTS devices. Thyristor Controlled Series Compensator (TCSC) and Static Var Compensator (SVC) are utilized to achieve the determined objectives. The problem is formulated according to Sequential Quadratic Programming (SQP) problem in the first stage. This formulation is used to accurately evaluate static security margin with congestion alleviation constraint incorporating voltage dependence of loads in the presence of FACTS devices and estimated annual load profile. The best trade-off between conflicting objectives has been obtained through Genetic Algorithm (GA) based fuzzy multi-objective optimization approach, in the next stage. The IEEE 14-bus test system is selected to validate the allocated devices for all load-voltage characteristics determined by the proposed approach. Congestion Alleviation,FACTS,Fuzzy,Genetic Algorithm,Optimal Location,Voltage Stability, http://ijeee.iust.ac.ir/article-1-84-en.html http://ijeee.iust.ac.ir/article-1-84-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 Stochastic Assessment of Voltage Sags in Distribution Networks 191 201 EN M. Aliakbar-Golkar Y Y. Raisee-Gahrooyi N This paper compares fault position and Monte Carlo methods as the most common methods in stochastic assessment of voltage sags. To compare their abilities, symmetrical and unsymmetrical faults with different probability distribution of fault positions along the lines are applied in a test system. The voltage sag magnitude in different nodes of test system is calculated. The problem with these two methods is that they require unknown number of iteration in Monte Carlo Method and number of fault position to converge to an acceptable solution. This paper proposes a method based on characteristic behavior of Monte Carlo simulations for determination required number of iteration in Monte Carlo method. Confidence Interval,Distribution Networks,Stochastic Methods,Voltage Sag, http://ijeee.iust.ac.ir/article-1-85-en.html http://ijeee.iust.ac.ir/article-1-85-en.pdf

Iran University of Science and Technology (IUST) Iranian Journal of Electrical and Electronic Engineering 1735-2827 1735-2827 4 4 2008 12 1 Dynamic Performance Analysis of Hysteresis Motors by a Linear Time-Varying Model 202 215 EN A. Darabi Y T. Ghanbari N M. Rafiei N H. Lesani N M. Sanati-Moghadam N Hysteresis motors are self starting brushless synchronous motors which are being used widely due to their interesting features. Accurate modeling of the motors is crucial to successful investigating the dynamic performance of them. The hysteresis loops of the material used in the rotor and their influences on the parameters of the equivalent circuit are necessary to be taken into consideration adequately. It is demonstrated that some of the equivalent circuit parameters vary significantly with input voltage variation and other operating conditions. In this paper, a comprehensive analysis of a hysteresis motor in the start up and steady state regimes are carried out based on a developed d-q model of the motor with time-varying parameters being updated during the simulation time. The equivalent circuit of the motor is presented taking into account the major impact of the input voltage. Simulation results performed in Matlab-Simulink environment prove that the existing simple models with constant parameters can not predict the motor performance accurately in particular for variable speed applications. Swings of torque, hunting phenomenon, improvement of power factor by temporarily increasing the stator voltage and start up behavior of the hysteresis machine are some important issues which can accurately be analyzed by the proposed modeling approach. Dynamic Transient Model,Equivalent Circuit,Hysteresis Motor,Variable Parameters, http://ijeee.iust.ac.ir/article-1-86-en.html http://ijeee.iust.ac.ir/article-1-86-en.pdf