Volume 5, Issue 3 (September 2009)
IJEEE 2009, 5(3): 180-184 |
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Abstract: (14584 Views)
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
Type of Study: Review Paper |
Subject:
Integrated Circuits: Digital, Analog
Received: 2009/09/08 | Accepted: 2013/12/30
Received: 2009/09/08 | Accepted: 2013/12/30
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