Volume 5, Issue 3 (September 2009)                   IJEEE 2009, 5(3): 180-184 | Back to browse issues page

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S. R. Talebiyan, S. Hosseini-Khayat. Low-Power Adder Design for Nano-Scale CMOS. IJEEE 2009; 5 (3) :180-184
URL: http://ijeee.iust.ac.ir/article-1-182-en.html
Low-Power Adder Design for Nano-Scale CMOS
S. R. Talebiyan , S. Hosseini-Khayat
Abstract:   (15000 Views)
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
Keywords: Nano-Scale CMOS Technology , Static Power Consumption , Adder Subcomponents
Full-Text [PDF 440 kb]   (7248 Downloads)    
Type of Study: Review Paper | Subject: Integrated Circuits: Digital, Analog
Received: 2009/09/08 | Accepted: 2013/12/30
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.