Volume 8, Issue 4 (December 2012)                   IJEEE 2012, 8(4): 290-302 | Back to browse issues page

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Masoumi M, Mahdizadeh H. A Novel and Efficient Hardware Implementation of Scalar Point Multiplier. IJEEE. 2012; 8 (4) :290-302
URL: http://ijeee.iust.ac.ir/article-1-502-en.html
Abstract:   (4064 Views)
A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with G = 55 our proposed design is able to compute GF(2163) elliptic curve scalar multiplication in 9.6 μs with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where G is the digit size of the underlying digit-serial finite field multiplier. Another implementation variant for less resource consumption is also proposed. With G=33, the design performs the same operation in 11.6 μs at 263 MHz on the same platform. The results of synthesis show that in the first implementation 17929 slices or 20% of the chip area is occupied which makes it suitable for speed critical cryptographic applications while in the second implementation 14203 slices or 16% of the chip area is utilized which makes it suitable for applications that may require speed-area trade-off. The new design shows superior performance compared to the previously reported designs.
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Type of Study: Research Paper | Subject: VLSI
Received: 2012/05/04 | Revised: 2012/12/31 | Accepted: 2012/12/26

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