Volume 14, Issue 3 (September 2018)                   IJEEE 2018, 14(3): 236-244 | Back to browse issues page


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Soleimani M, Toofan S. High-Speed and Low-Power Flash ADCs Encoder. IJEEE. 2018; 14 (3) :236-244
URL: http://ijeee.iust.ac.ir/article-1-1181-en.html
Abstract:   (620 Views)
This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-input compound AND-OR gates. In the second stage by two ROM encoders, 2-of-M codes determine n-1 MSB bits and one LSB bit. The advantages of the proposed encoder rather than other similar works are high speed, low power consumption, low active area, and low latency with same bubble error removing capability. To demonstrate the mention specifications, 5-bit flash ADCs with conventional and proposed encoders in their encoder blocks, are simulated at 2-GS/s and 3.5-GS/s sampling rates in 0.18-μm CMOS process. Simulation results show that the ENOB of flash ADCs with conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined almost 30-ps faster rather than the conventional encoder at 2-GS/s. Also, the power consumptions of the conventional and proposed encoders were 17.94-mW and 11.74-mW at 3.5-GS/s sampling rate from a 1.8-V supply, respectively. Corresponding, latencies of the conventional and proposed encoders were 3 and 2 clock cycles. In this case, number of TSPC D-FFs and logic gates of the proposed encoder is decreased almost 39% compared to the conventional encoder.
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Type of Study: Research Paper | Subject: Microelectronics
Received: 2017/10/20 | Accepted: 2018/02/16 | Published: 2018/02/16