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Abstract:   (331 Views)
Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive number of combinations of waveform shapes, which can be applied to the input ports of logic gates, causes existing lookup-based methods to have huge space requirements. In this article, instead of considering all possible combinations of waveform shapes in the characterization phase of delay calculation process, the least number of combinations, which are dominant in determining the waveform shape of gate output, is presented. Multivariate Polynomial Regression (MPR) method is used to further reduce the required memory space. Exploration on the possible MPR analyses is performed to find the best regression case with proper memory space reduction and precision. Attained results shows a 1.013E6 times reduction in storage space required for storing parameters utilized in extraction of output waveform characteristics in comparison to a state of the art work, accompanied by acceptable precision.
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Type of Study: Research Paper | Subject: Devices & Circuits Modeling & Simulation
Received: 2019/03/02 | Accepted: 2019/04/27 | Published: 2019/04/27

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© 2019 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.