Volume 16, Issue 4 (December 2020)                   IJEEE 2020, 16(4): 487-493 | Back to browse issues page

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Pinto R. Modified 32-Bit Shift-Add Multiplier Design for Low Power Application. IJEEE 2020; 16 (4) :487-493
URL: http://ijeee.iust.ac.ir/article-1-1782-en.html
Modified 32-Bit Shift-Add Multiplier Design for Low Power Application
R. Pinto
Abstract:   (3048 Views)
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. The multiplier speed usually determines the speed of the processor. Hence in this work, a design of a 32-bit multiplier is proposed by modifying the conventional shift-add multiplier. The proposed structure reduces the power consumed by the technique of minimizing the switching activities in the design. A 32-bit parallel prefix adder based on the modified Ling equation is also proposed to speed up the addition of the partial products in the multiplier. The design is modeled in VHDL and implementation is carried out in CADENCE software with 90 nm and 180 nm CMOS technology.
Keywords: Shift-Add Multiplier , Parallel Prefix Adder , Low-Power , VLSI Implementation
Full-Text [PDF 676 kb]   (2128 Downloads)    
Type of Study: Research Paper | Subject: VLSI
Received: 2020/01/18 | Revised: 2020/03/12 | Accepted: 2020/03/16
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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.