Volume 22, Issue 4 (December 2026)                   IJEEE 2026, 22(4): 3808-3808 | Back to browse issues page

XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
ingle B, Nemade M. A Comprehensive Assessment of Random Number Generators on FPGA: Emerging Techniques, Challenges & Future Scope. IJEEE 2026; 22 (4) :3808-3808
URL: http://ijeee.iust.ac.ir/article-1-3808-en.html
A Comprehensive Assessment of Random Number Generators on FPGA: Emerging Techniques, Challenges & Future Scope
Bhagyashree Ingle , Milind Nemade
Abstract:   (780 Views)
The computing paradigm has perceived a logical shift from CPU towards application-specific GPU, FPGA, and CPLD due to slowdown of Moore’s Law, operating system overheads, serial data processing, memory management, power efficiency, and speed. The performance increase of general-purpose CPUs & GPUs is unable to match the advances in peripheral interfaces; reconfigurable logic deployed in FPGAs provides several exceptional properties that may be able to deliver the desired performance. FPGA-based digital circuits provide an intermediate arrangement between ASIC and CPU in terms of throughput, latency, portability, and design time. True random number generators (TRNG) are expensive, have low bandwidth and speed, and are incompatible with FPGA or heterogeneous architectures. Therefore, the design and development of alternative and affordable random-number generators is the focus of several researchers. TRNG design in FPGAs is more challenging because it must meet low power and area, high speed, and throughput requirements without compromising the statistical quality of the desired results for intended applications. In this paper, an attempt has been made to highlight emerging techniques and challenges associated with FPGA implementation of a random number generator. Furthermore, forthcoming techniques with the use of heterogeneous computation with FPGA and Python productive multiprocessor system-on-chip (MPSoC) architecture for generation of random numbers are discussed.
Keywords: True random number generator (TRNG), Field programmable gate array (FPGA), Metastability, Heterogeneous computing, Machine learning resistant.
Full-Text [PDF 724 kb]   (199 Downloads)    
Type of Study: Review Paper | Subject: VLSI
Received: 2025/03/12 | Revised: 2026/08/30 | Accepted: 2026/01/28
Rights and permissions
Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
Creative Commons License
© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.