Volume 8, Issue 1 (March 2012)                   IJEEE 2012, 8(1): 16-27 | Back to browse issues page

XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Masoumi M. Differential Power Analysis: A Serious Threat to FPGA Security. IJEEE. 2012; 8 (1) :16-27
URL: http://ijeee.iust.ac.ir/article-1-385-en.html
Abstract:   (3830 Views)
Differential Power Analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher key. Cryptographic security gets compromised if the current waveforms obtained correlate with those from a hypothetical power model of the circuit. As FPGAs are becoming integral parts of embedded systems and increasingly popular for cryptographic applications and rapid prototyping, it is imperative to consider security on FPGAs as a whole. During last years, there has been a large amount of work done dealing with the algorithmic and architectural aspects of cryptographic schemes implemented on FPGAs, however, there are only a few articles that assess their vulnerability to such attacks which, in practice, pose far a greater danger than algorithmic attacks. This paper first demonstrates the vulnerability of the Advanced Encryption Standard Algorithm (AES) implemented on a FPGA and then presents a novel approach for implementation of the AES algorithm which provides a significantly improved strength against differential power analysis with a minimal additional hardware overhead. The efficiency of the proposed technique was verified by practical results obtained from real implementation on a Xilinx Spartan-II FPGA.
Full-Text [PDF 729 kb]   (2687 Downloads)    
Type of Study: Research Paper | Subject: Signal Processing
Received: 2011/04/05 | Accepted: 2012/02/04 | Published: 2013/12/30