Abstract: (11277 Views)
In this paper a new synthesis for circuit design of Euclidean distance calculation
is presented. The circuit is implemented based on a simple two-quadrant squarer/divider
block. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak
inversion region, features low circuit complexity, low power (<20uW), low supply voltage
(0.5V), two quadrant input current, wide dynamic range and immunity from body effect. In
addition, this circuit is designed in modular methodology, leading to a very regular
structure. The circuit was successfully applied to the recognition of some simple patterns.
Simulation results of the circuit by HSPICE show high performance in the separation and
confirm the validity of the proposed technique.
Type of Study:
Research Paper |
Received: 2009/03/16 | Accepted: 2009/03/16