Volume 16, Issue 4 (December 2020)                   IJEEE 2020, 16(4): 439-448 | Back to browse issues page

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Razavi S M, Razavi S M. A Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates. IJEEE 2020; 16 (4) :439-448
URL: http://ijeee.iust.ac.ir/article-1-1647-en.html
A Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates
S. M. Razavi , S. M. Razavi
Abstract:   (2592 Views)
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circuits. First, excessive hardware overhead that imposes a great cost, power consumption and propagation delay on the circuits and second, separate implementation of feedback lines that adds further delay to the circuits. In this paper, we propose a novel approach for minimal-cost inherent-feedback implementation of low-power MRF-based logic gates. The simulation results, which are based on 32nm BSIM4 models, demonstrate that besides excellent noise immunity of the proposed method, it has the least propagation delay in comparison with all of the previously reported MRF-based gates due to its inherent feedbacks. In addition, the proposed method outperforms competing ones, which have comparable noise immunity, in other circuit metrics like cost and power consumption. Specifically, the proposed method achieves at least 18%, 29%, and 39% reductions in cost, delay and power consumption with considerable noise immunity improvement compared with competing methods.
Keywords: Noise Tolerance , Markov Random Field (MRF) , Noise Immunity , Reliability
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  • The proposed method demonstrates the least propagation delay among all of the previously reported MRF-based methods.
  • This is the first work that achieves high levels of noise immunity with considerably low cost, delay, and power consumption.
  • We introduce the feedback inherency notion into the MRF-based logic gates’ design.
  • The proposed method shows the least cost, delay, and power in comparison with competing methods that have comparable noise immunity.

Type of Study: Research Paper | Subject: VLSI
Received: 2019/10/08 | Revised: 2019/11/27 | Accepted: 2019/11/29
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.