Volume 17, Issue 3 (September 2021)                   IJEEE 2021, 17(3): 1730-1730 | Back to browse issues page

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Abolmaali S. Area Reduction of Combinational Circuits Considering Path Sensitization. IJEEE 2021; 17 (3) :1730-1730
URL: http://ijeee.iust.ac.ir/article-1-1730-en.html
Area Reduction of Combinational Circuits Considering Path Sensitization
S. Abolmaali
Abstract:   (2230 Views)
Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
Keywords: Area Reduction , Gate Resizing , Path Sensitization , Timing Analysis , Viability Analysis
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  • Study of gate delay changes on altering the viability of circuit paths.
  • Proposing a complete path-based algorithm of gate resizing which utilizes viability analysis in the selection of candidate nodes.
  • Decreasing the size of all circuit gates at the beginning of the proposed method and then increasing the size of circuit gates which violate the circuit timing constraint, instead of using gate slacks.
  • Introducing an incremental algorithm for gate resizing which uses previously-obtained not-altered viabilities of circuit paths.
  • Proposing a proper metric, based on viability conditions, to select the best nodes to become a candidate for resizing.

Type of Study: Research Paper | Subject: VLSI
Received: 2019/11/28 | Revised: 2021/01/11 | Accepted: 2021/01/15
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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.