Volume 17, Issue 1 (March 2021)                   IJEEE 2021, 17(1): 1809-1809 | Back to browse issues page

XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Kulkarni P, Hogade B, Kulkarni V. ASIC Design of Butterfly Unit Based on Non-Redundant and Redundant Algorithm. IJEEE 2021; 17 (1) :1809-1809
URL: http://ijeee.iust.ac.ir/article-1-1809-en.html
ASIC Design of Butterfly Unit Based on Non-Redundant and Redundant Algorithm
P. Kulkarni , B. Hogade , V. Kulkarni
Abstract:   (2531 Views)
Fast Fourier Transform (FFT) processors employed with pipeline architecture consist of series of Processing Elements (PE) or Butterfly Units (BU). BU or PE of FFT performs multiplication and addition on complex numbers. This paper proposes a single BU to compute radix-2, 8 point FFT in the time domain as well as frequency domain by replacing a series of PEs. This BU comprises of fused floating point (FP) addition-subtraction (FFAS) and modified booth algorithm based floating point multiplier (FMULT). BU performs all arithmetic operations in floating pointform to overcome the nonlinearities available in fixed word length (FWL). FP arithmetic is slower as compared with FWL. To improve the speed of operation, symmetrical property of twiddle constant is used and they are embedded in the BU. BU outputs two halves of computation simultaneously with a single FFAS and two FMULT. BU design is synthesized, placed and routed for 45nm technology of nangate open cell library. Synthesized results show that proposed BU consumes 23910µm2 area with latency of 3.44ns which are 5.05% smaller in area, 7.02% faster and replaces a set of two five operand adder and two multipliers by a single FFAS as compared with previously reported smallest work.
Keywords: Binary Signed Digit , Butterfly Unit , Carry Free Addition , Fast Fourier Transform , Fused Floating Point Addition-Subtraction
Full-Text [PDF 803 kb]   (948 Downloads)    
  • Single BU replaces Series of processing elements in the pipeline architecture of the FFT processor.
  • The design has less area consumption.
  • Suitable for DIF as well as DIT computation.
  • Small independent computation.

Type of Study: Research Paper | Subject: VLSI
Received: 2020/02/14 | Revised: 2020/04/06 | Accepted: 2020/04/10
Rights and permissions
Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
Creative Commons License
© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.