Volume 17, Issue 3 (September 2021)                   IJEEE 2021, 17(3): 1857-1857 | Back to browse issues page

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Gudey S K, Andavarapu S. Grid Interconnection of Solar and Battery System Using an Asymmetrical T-Type Multilevel Inverter to improve Conversion Efficiency with Reduced THD. IJEEE 2021; 17 (3) :1857-1857
URL: http://ijeee.iust.ac.ir/article-1-1857-en.html
Grid Interconnection of Solar and Battery System Using an Asymmetrical T-Type Multilevel Inverter to improve Conversion Efficiency with Reduced THD
S. K. Gudey , S. Andavarapu
Abstract:   (2742 Views)
A three-phase dual-port T-type asymmetrical multilevel inverter (ASMLI) using two sources, solar forming the high voltage level and the battery forming the low voltage level, is considered for grid interconnection. A vertical shifted SPWM is used for the ASMLI circuit. A transformerless system for grid interconnection is achieved for a 100-kW power range. A well-designed boost converter and a Buck/Boost converter is used on the front side of the inverter. Design of battery charge controller and its controlling logic are done and its SOC is found to be efficient during charging and discharging conditions. A closed-loop control using PQ theory is implemented for obtaining power balance at 0.7 modulation index. The THD of the current harmonics in the system is observed to be 0.01% and voltage harmonics is 0.029% which are well within the permissible limits of IEEE-519 standard. The power balance is found to be good between the inverter, load, and the grid during load disconnection for a period of 0.15s. A comparison of THD’s, voltage, current stresses on the switches, and conduction losses is also presented for a single-phase system with respect to a two-level inverter which shows improved efficiency and low THD. Hence this system can be proposed for use in grid interconnection with renewable energy sources.
Keywords: Asymmetrical Multilevel , Battery , Efficiency , Solar , THD
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  • A three-phase dual-port T-type Asymmetrical multilevel inverter (DP-ASMLI) using two sources, high voltage level from solar and the battery forming the low voltage level is considered for grid interconnection.
  • The system performs a transformerless operation for grid interconnection of 100kW range.
  • A vertical shifted SPWM is used for the ASMLI circuit. A closed-loop control using PQ theory is implemented for obtaining power balance at 0.7 modulation index.
  • Design of front end converter, inverter, and the filter parameters are addressed.
  • The THD of the current harmonics present in the system is 0.01% and voltage harmonics is 0.029% which is well within the permissible limits of IEEE-519 standard.
  • A comparison of THD’s, voltage, current stresses on the switches, and conduction losses are presented for a single-phase system w. r. t. a two-level inverter which shows improved efficiency and low THD for use in grid interconnection with renewable energy sources.
  • The power balance between the inverter to load and the grid for load sharing is efficient.
  • It is observed that the T-type inverter is a better replacement for the conventional H-bridge inverter for grid interconnection.
  • The work can be extended with other renewable energy sources with different control algorithms. The DC-DC converters of the latest methodology (sepic/interleaved boost) also can be included.
  • The battery charge controller can be understood with the latest algorithms.
  • This inverter finds application in back-back inter tie, induction heating, Reactive power compensation, adjustable speed drives, UPS, etc.

Type of Study: Research Paper | Subject: Active and Reactive Power Converter Control
Received: 2020/04/14 | Revised: 2020/12/26 | Accepted: 2021/01/15
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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.