Volume 17, Issue 4 (December 2021)                   IJEEE 2021, 17(4): 2011-2011 | Back to browse issues page


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Pathan A, Memon T. FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems. IJEEE 2021; 17 (4) :2011-2011
URL: http://ijeee.iust.ac.ir/article-1-2011-en.html
Abstract:   (1825 Views)
FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.
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Type of Study: Research Paper | Subject: VLSI
Received: 2020/10/12 | Revised: 2021/04/08 | Accepted: 2021/04/25

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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.