Volume 18, Issue 1 (March 2022)                   IJEEE 2022, 18(1): 2238-2238 | Back to browse issues page

XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Mendez T, Nayak S G. Design and Analysis of an Iterative Carry Save Adder-based Power-Efficient Multiplier. IJEEE 2022; 18 (1) :2238-2238
URL: http://ijeee.iust.ac.ir/article-1-2238-en.html
Design and Analysis of an Iterative Carry Save Adder-based Power-Efficient Multiplier
T. Mendez , S. G. Nayak
Abstract:   (1878 Views)
The need for low-power VLSI chips is ignited by the enhanced market requirement for battery-powered end-user electronics, high-performance computing systems, and environmental concerns. The continuous advancement of the computational units found in applications such as digital signal processing, image processing, and high-performance CPUs has led to an indispensable demand for power-efficient, high-speed and compact multipliers. To address those low-power computational aspects with improved performance, an approach to design the multiplier using the algorithms of Vedic math is developed in this research. In the proposed work, the pre-computation technique is incorporated that aided in estimation of the carries during the partial product calculation stage; that enhanced the speed of the multiplier. This design was carried out using Cadence NCSIM 90 nm technology. The comparative analysis between the proposed multiplier design and the multipliers from the literature resulted in a substantial improvement in power dissipation as well as delay. The research was extended to assess the designed architectures’ performance statistically, applying the independent sample t-test hypothesis.
Keywords: Low-Power , Multiplier , Pre-Computation , VLSI Implementation
Full-Text [PDF 1553 kb]   (1187 Downloads)    
  • A new method of iterative carry-save adder is proposed in the design of the Vedic multiplier thereby enhancing the speed;
  • The pre-computation technique is used in the design of the Vedic multiplier;
  • The proposed multiplier demonstrates significant power and speed results over conventional multipliers;
  • The statistical analyses of the designed architecture were analyzed by using an independent sample t-test hypothesis.

Type of Study: Research Paper | Subject: VLSI
Received: 2021/07/14 | Revised: 2021/09/25 | Accepted: 2021/10/04
Rights and permissions
Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
Creative Commons License
© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.