Volume 19, Issue 1 (March 2023)                   IJEEE 2023, 19(1): 2391-2391 | Back to browse issues page

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Samanth R, Nayak S G, Nempu P B. A Novel Multiply-Accumulator Unit Bus Encoding Architecture for Image Processing Applications. IJEEE 2023; 19 (1) :2391-2391
URL: http://ijeee.iust.ac.ir/article-1-2391-en.html
A Novel Multiply-Accumulator Unit Bus Encoding Architecture for Image Processing Applications
R. Samanth , S. G. Nayak , P. B. Nempu
Abstract:   (1401 Views)
In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the development of MAC unit bus encoders as well as the identification of an improved architecture for image processing applications. To reduce the power consumption in these functional units, two bus encoding architectures were developed by encoding data before it was sent on the data buses. One is MSB reference encoding, and another is Fourth and Fifth bit ANDing (FFA) without the need for an extra bus line with fewer transitions by using gray codes. The comparison of the proposed encoding architectures with the existing encoding architectures from the literature revealed an 8% to 36% significant improvement in power dissipation. The simulation was done with Xilinx ISE, and the Cadence RTL Compiler tool was utilized for the synthesis, which was done with the 180nm technology library. And also, the image filtering is analyzed using MATLAB.
Keywords: Data Bus Encoders , Fourth and Fifth Bit ANDing , Gaussian Filter , MSB Reference Encoding , Multiply-Accumulator Unit
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  • Two encoder architectures called MSB reference, Fourth and Fifth bit ANDing (FFA) are developed to improve the power efficiency.
  • Gray codes are employed to avoid multiple bit transition problems as well as synchronization problems when the values are passing from one clock domain to another.
  • A Novel Multiply-Accumulate unit (MAC) is proposed by integrating these encoder blocks to achieve low power consumption.
  • The proposed MAC unit bus encoder architecture is applied on 2D Gaussian blurring technique and the results are validated in the MATLAB platform.

Type of Study: Research Paper | Subject: VLSI
Received: 2022/01/14 | Revised: 2023/02/23 | Accepted: 2022/09/28
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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.