Iranian Journal of Electrical and Electronic Engineering
Iran University of Science and Technology
Mon, Jul 15, 2024
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Volume 7, Issue 2 (June 2011)
IJEEE 2011, 7(2): 112-121 |
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Rana A, Chand N, Kapoor V. A Novel Hybrid Nano Scale MOSFET Structure for Low Leak Application. IJEEE 2011; 7 (2) :112-121
URL: http://ijeee.iust.ac.ir/article-1-357-en.html
URL: http://ijeee.iust.ac.ir/article-1-357-en.html
Abstract: (7506 Views)
In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leakage behaviour of HMOS has been investigated with the help of compact analytical model and Sentaurus Simulation. The results so obtained show good agreement between model and simulation data. It is found that HMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped MOSFET structure. Further, the proposed structure had demonstrated improved on current, off current, subthreshold slope and DIBL characteristic.
Keywords: Hybrid MOSFET(HMOS) , Gate Tunneling Current , Analytical Model , Spacer Dielectrics , DIBL , Subthreshold Slope
Type of Study: Research Paper |
Subject:
Semiconductor Devices
Received: 2010/12/20 | Revised: 2011/12/24 | Accepted: 2011/06/18
Received: 2010/12/20 | Revised: 2011/12/24 | Accepted: 2011/06/18
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