Volume 7, Number 2 (June 2011)                   IJEEE 2011, 7(2): 112-121 | Back to browse issues page


XML Print


Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Rana A, Chand N, Kapoor V. A Novel Hybrid Nano Scale MOSFET Structure for Low Leak Application. IJEEE. 2011; 7 (2) :112-121
URL: http://ijeee.iust.ac.ir/article-1-357-en.html

Abstract:   (3756 Views)
In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leakage behaviour of HMOS has been investigated with the help of compact analytical model and Sentaurus Simulation. The results so obtained show good agreement between model and simulation data. It is found that HMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped MOSFET structure. Further, the proposed structure had demonstrated improved on current, off current, subthreshold slope and DIBL characteristic.
Full-Text [PDF 362 kb]   (1448 Downloads)    
Type of Study: Research Paper | Subject: Semiconductor Devices
Received: 2010/12/20 | Accepted: 2011/06/18 | Published: 2013/12/30

Add your comments about this article : Your username or email:
Write the security code in the box

© 2015 All Rights Reserved | Iranian Journal of Electrical and Electronic Engineering

Designed & Developed by : Yektaweb