XML Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Ashraf M. Switched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications. IJEEE. 2018;
URL: http://ijeee.iust.ac.ir/article-1-1122-en.html
Abstract:   (238 Views)
This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of a PMOS transistor. The proposed structure improves the propagation delay of a circuit and is much suitable for those circuits with high switching factor. Post layout simulation results using TSMC 180nm CMOS technology at 0.2V supply voltage shows 45% improvement in delay as well as 25% less power consumption at the cost of only 53% more occupied area.
Full-Text [PDF 1986 kb]   (42 Downloads)    
Type of Study: Research Paper | Subject: Integrated Circuits: Digital, Analog
Received: 2017/07/08 | Accepted: 2017/12/19 | Published: 2017/12/29