Volume 20, Issue 2 (June 2024)                   IJEEE 2024, 20(2): 2955-2955 | Back to browse issues page

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Ahangari Z. Design and Performance Optimization of a Bi-Channel Ge-GaAs Vertical Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate. IJEEE 2024; 20 (2) :2955-2955
URL: http://ijeee.iust.ac.ir/article-1-2955-en.html
Abstract:   (293 Views)
In this paper, an innovative vertical bi-channel tunnel field effect transistor is presented that exploits line tunneling mechanism to achieve improved electrical performance. In this device, the source contains germanium, while the channel and drain regions consist of GaAs., which results in a type-II heterostructure with low resistance tunneling barrier. The source region is situated in a vertical position, enclosed by two sidewall channels that encompass a broad area of tunneling. Our proposed design effectively blocks the electric field that is originated from the drain at the tunneling junction, thereby conferring high immunity to drain induced barrier thinning effect. The device that has been suggested offers a significantly greater on-state current, a factor of 144, when compared to the traditional TFET and provides a subthreshold swing of 3mV/dec and an on/off current ratio of 9.76×1010. According to statistical analysis, the design parameters of metal gate workfunction value and source doping concentration are crucial and have the potential to impact device performance. Therefore, selecting the appropriate combination of these parameters is essential. The proposed device serves as a foundation for the development of computing systems that are low in power and high in speed.
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Type of Study: Research Paper | Subject: Semiconductor Devices
Received: 2023/07/01 | Revised: 2024/05/25 | Accepted: 2024/05/04

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.