Volume 22, Issue 3 (September 2026)                   IJEEE 2026, 22(3): 4056-4056 | Back to browse issues page

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Vijaya Babu E, Shanthi G, Thabassum Ara A, Balaramakrishna K V, Nakirekanti M, Narsimha Reddy K. Power-Gated Memristor-Based Optimized PIPO Shift Register. IJEEE 2026; 22 (3) :4056-4056
URL: http://ijeee.iust.ac.ir/article-1-4056-en.html
Power-Gated Memristor-Based Optimized PIPO Shift Register
E Vijaya Babu , G Shanthi , Ayesha Thabassum Ara , K V Balaramakrishna , Madhu Nakirekanti , K Narsimha Reddy
Abstract:   (129 Views)
Memristors are a viable future semiconductor memory substitute because of its nanoscale size, quick switching, low power consumption, and CMOS compatibility. CMOS flip-flops face drawbacks like large size, high power use, and charge loss at smaller scales. However, memristors provide a novel approach to the construction of FFs that improves outcomes. In the previous work, the execution of a four-bit PIPO shift register design was demonstrated using a D flip-flop. D Flip-flops are designed with NAND Gates. In this paper, we will improve the performance of flip-flops by using memristors, followed by the performance of D flip-flops and PIPO shift register using the Power Gating Technique. As the Results Session displays the power usage of the NAND Gate. The power consumption of a D flip-flop using the memristor design is 6.182 µW, while using the power gating technique, the power usage of D flip-flop is 5.827 µW. For DFF Power reduced by 86.1%, Delay reduced by 47.1% and PDP improved by 99.86% compared to conventional design. The power consumption of a PIPO using the memristor design is 22.52 µW, while using the power gating technique, the power usage of PIPO is 21.28 µW. The power consumption of PIPO circuit is reduced by 98.3% compared with conventional design.
 
Keywords: Flip-flops, NAND Gate, Memristor, Power Gating, Parallel in parallel Out
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Type of Study: Research Paper | Subject: VLSI
Received: 2025/07/23 | Revised: 2026/05/01 | Accepted: 2025/12/27
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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.